1. Field of the Invention
The present invention relates to a memory device, and more particularly, a charge gain stress test (CGSL) circuit for a memory device and a test method using the same.
2. Background of the Related Art
Generally, a CGST circuit tests an inflow of unwanted electrons to a floating gate through a tunnel oxide for memory devices, such as nonvolatile memories including a flash memory. A ground source voltage VSS is applied to the source and drain, e.g., of a flash memory cell and then a voltage (a stress voltage) higher than an operating voltage is applied for a predetermined time to a gate. The high voltage applied to the gate is inversely proportional to the time for applying the stress. Thus, when the voltage is high, the stress time is shorter compared to when the voltage is low, where the stress time is longer.
FIG. 1 illustrates a related CGST circuit for a flash memory. A reference current generating unit 1 generates a reference current Iref, and a sense amp 2 outputs a compare result SOUT by comparing the reference current Iref with a cell current Icell. A flash memory cell 3 includes a floating gate and a source, which is connected with a ground source voltage VSS. A first switch SW1 is controlled by a first control signal READ and selectively connects the drain to the sense amp 2 or the ground source voltage VSS and a second switch SW2 selectively connects the gate of the flash memory 3 to a stress voltage Vpps controlled by the first control signal READ, which is used for the stress application, or a read voltage Vppr used for reading a cell state.
In such a CGST circuit, the first switch SW1 connects the drain of the flash memory cell 3 with the sense amp 2 in accordance with the first control signal READ, and the second switch SW2 connects the gate of the flash memory cell 3 with the read voltage Vppr. The sense amp 2 compares the cell current Icell flowing into the flash memory cell 3 with the reference current Iref to thereby output the compare result SOUT. The output signal SOUT from the sense amp 2 could be "1" or "0" depending upon the design of the circuit. For example, when the cell current Icell is greater than the reference current Iref, the sense amp 2 may output "1" as the output signal SOUT based on the design of the circuit.
The first switch SW1 controlled by the first control signal READ connects the drain of the flash memory cell 3 to the ground source voltage VSS and the second switch SW2 applies the stress voltage Vpps to the gate of the flash memory cell 3 for thereby applying the stress thereto for a predetermined period of time. After applying the stress for the predetermined period of time, the first switch SW1 connects the drain of the flash memory cell 3 to the sense amp 2, and the second switch SW2 connects the gate of the flash memory cell 3 to the read voltage Vppr.
If the flash memory cell 3 has an inferior characteristic, and thus electric electrons flow excessively into the floating gate due to the stress, the sense amp 2 outputs "0" because the cell current Icell is smaller than the reference current Iref. If the volume of the electrons flowing into the floating gate is very small, the sense amp 2 outputs "1" because the cell current Icell is still greater than the reference current Iref. If the output signal SOUT from the sense amp 2 is "0" according to such a CGST test, the cell is determined to be in a weak condition.
If directly testing a unit cell by an external device, it is necessary to consider the size of the voltage applied to gate, drain and source. However, in case of making and operating an array by using a circuit installing cells, the size of the voltage applied to each terminal is limited by characteristics of devices and peripheral circuits. In other words, the characteristics of the peripheral circuit and the devices limit the maximum applicable size of the voltage.
Accordingly, since the time for applying the stress is inversely proportional to the applied voltage, there is a limit to reduce the time for applying the stress. When having a chip constituting the nonvolatile memory cell as the array, since there occurs the limitation to the maximum applicable voltage due to the characteristics of the peripheral circuit and the devices, the stress application time, namely the test time, can not be reduced below a specific time, which results in a longer test time. In addition, since the voltage applied to the stress is considerably higher than the operating voltage in the normal operation, a serious burden is placed upon the peripheral circuit unit.